Computer systems typically include a central processing unit or CPU, a memory subsystem, and input/output devices, including but not limited to a mouse, a keyboard, disk drives, a display unit, a printer and possibly connections to a network. Many systems further include a plurality of processors or CPUs. Most systems also include a second level cache memory subsystem, or L2 cache, which is designed to include a limited but faster memory than a main system memory for storage of information which is accessed more frequently than other information which may be stored in the relatively slower system main memory. All of these components are typically connected together through a local bus system which has direct connections to the L2 cache as well as to the main system memory.
Many CPU units have the capability to process so-called "burst" access grants to various components within a computer system. When a burst access is initiated, the main system memory is able to read or write longer streams of information than normal without being interrupted by subsequent requests for access to different addresses in main memory from different computer system components. This burst mode is effective to increase the processing speed of a system, especially when large amounts of information are being processed, since larger segments of the information can be transferred in single bursts without intervening wait states, and memory arbitration and access delays, which would otherwise be incurred in transferring smaller segments of information in iterative successive sequences.
Typically, accesses to memory are controlled by a system memory controller which usually includes memory access request arbitration circuitry designed to sort out various requests for access to the main system memory by various components of the computer system, and to grant requests in a grant order calculated to most effectively and expeditiously transfer the requested information. In general, the priorities for the memory controllers, and included arbitration circuits, are relatively well established to optimize information flow into and out of system main memories. However, there has been little if any improvement in the optimization of information transfer into and out of the relatively faster cache memory subsystems of computer systems. Moreover, even improved cache memory systems are limited by the existing schemes for arbitrating and controlling system memory access requests on a system level. Accordingly, there is a need for an improved arbitration device and cache memory, including a cache memory access arbitration technique capable of enabling a faster transfer of information between cache memory and computer system components requesting access to information stored in the cache.